I. INTRODUCTION

Ambipolar transistors have emerged as one of the most promising devices to simplify the whole process flow of complementary metal-oxide-semiconductor (CMOS) logic integrated circuits. Depending on the bias conditions, ambipolar transistors can function in both hole-dominated p-type and electron-dominated n-type modes. A single ambipolar device incorporating both p- and n-type performances enables complementary-like operation and can replace p- or n-channel unipolar MOSFETs with a single ambipolar device ^[1-4]. Especially, for memory applications, because each unipolar mode of ambipolar transistors can be controlled independently, a large memory window can be achieved ^[1]. However, most of the previously-proposed ambipolar transistors adopt solution-process-based materials such as organic semiconductors, carbon nanotubes, and conjugated polymers. They suffer from the following practical problems: 1) difficulty in finding the electrodes for efficient electron/hole injection, 2) incompatibility with standard CMOS process, and 3) power dissipation increase and performance degradation due to leakage current ^[1-4].

To overcome the abovementioned challenges, tunnel field-effect transistors (TFETs) with ambipolar characteristics have been considered as an alternative ^[5-7]. In contrast to solution-process-based ambipolar FETs, TFETs feature the following advantages: 1) well-balanced electron- and hole-transport properties, 2) good CMOS process compatibility, and 3) extremely low leakage current and subthreshold swing ^[5-9]. Fig. 1 illustrates the structure of a planar SiGe homojunction TFET. Fig. 2 shows the lateral surface energy band diagrams from the source to drain. As the source and drain regions are doped with p-type and n-type dopants, respectively, TFETs can conduct both holes and electrons through their surface channels. When both gate voltage (V$_{\mathrm{G}}$) and drain voltage (V$_{\mathrm{D}}$) are positive, drain current (I$_{\mathrm{D}}$) is dominated by the electrons injected through the source-to-channel junction. On the contrary, when both V$_{\mathrm{G}}$ and V$_{\mathrm{D}}$ become negative, I$_{\mathrm{D}}$ is dominated by the holes injected through the drain-to-channel junction. This ambipolar conduction becomes prominent when the power supply voltage (V$_{\mathrm{DD}}$) or V$_{\mathrm{D}}$ is higher than E$_{\mathrm{G}}$/q (E$_{\mathrm{G}}$: bandgap, q: elementary charge) ^[7]. Also, in the off state, while a large tunneling barrier blocks any carrier injection, low-level leakage current is generated by the Shockley-Read-Hall (SRH) generation near the source and drain and by the direct or trap-assisted tunneling (TAT) from the source to drain ^[7].

However, because band-to-band tunneling (BTBT) is a major carrier injection mechanism whose probability is low, silicon TFETs have faced the problem with low current drivability ^[6-9]. Previous studies improved this issue by adopting silicon-germanium (SiGe) channel, source, and drain owing to the smaller band gap and consequent enhanced BTBT rate than silicon ^[6-10].

Even if SiGe-TFET-based logic applications have been studied intensively in previous works, most of them utilized TFETs as unipolar devices while suppressing the ambipolar current. In this manuscript, we investigate the effect of Ge mole fraction variation on the ambipolar characteristics of SiGe TFETs by using device and circuit simulation.

Fig. 1. Schematic of a planar homojunction SiGe TFET.

Fig. 2. Schematic of the ambipolar behavior of TFETs: (a) P-channel ambipolar state; (b) off state; (c) n-channel turn-on state.

II. SIMULATION ENVIRONMENTS

Device simulations were conducted using a commercial technology computer-aided design (TCAD) simulator ^[11]. Table 1 summarizes the simulated device parameters regarding the dimension and material properties. To obtain the symmetric I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ curves, source and drain doping concentrations are made equal. Table 2 summarizes the device simulation models such as Fermi statistics, non-local BTBT, and bandgap modulation owing to the high doping concentration in the source and drain regions. The BTBT parameters of Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ as a function of Ge mole faction (x) refer to the literature. For a particular electric field F, the BTBT generation rate G is given as follows ^[12]:

For x ${\leq}$ 0.5, the indirect tunneling process is dominant and F$_{0}$ = 1 V/cm, P = 2.5 ^[12]. The indirect BTBT parameters are A = 3.29${\times}$10$^{15}$, 2.61${\times}$10$^{15}$, 2.27${\times}$10$^{15}$ [cm$^{-3}$·s$^{-1}$] and B = 23.8, 18.1, 15.5 [MV·cm$^{-1}$] for x = 0, 0.3, 0.5 of Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ materials, respectively ^[12].

For channel materials, unstrained Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ is assumed where strain is relieved due to interfacial dislocations as shown in Fig. 3(a). The conduction band offset (${\Delta}$E$_{\mathrm{c}}$) values and the valence band offset (${\Delta}$E$_{\mathrm{v}}$) values between the Si and Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ are indicated in the band diagrams ^[12,13]. In the other case, Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ pseudomorphically grown on Si can be compressively strained as shown in Fig. 3(b) ^[14,15]. While the higher x value of Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ and strain reduce bandgap energy, it is widely known that the most band offset between the Si to Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ layer occurs in the valence band, which is called a type-Ⅱ staggered junction ^[14].

Although a SiGe-on-insulator (SGOI) layer is formed uniformly with the same Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ material, only the surface region near the source- and drain-to-channel junctions affects the TFET on-current ^[10]. In this work, the Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ whose x is {\textless} 0.5 is simulated. In this range, the following two characteristics are observed: 1) stronger indirect tunneling than direct tunneling ^[12] and 2) pure interfacial SiO$_{2}$ formed by thermal oxidation by rejecting Ge ^[16]. Also, regarding the interface trap density (D$_{\mathrm{it}}$), the high D$_{\mathrm{it}}$ is one of the major challenges on Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$-based CMOS devices. Nevertheless, it was reported in the previous study that D$_{\mathrm{it}}$ can be reduced to 2 ${\times}$10$^{11}$ cm$^{-2}$ by applying defect elimination techniques ^[17].

Fig. 3. (a) Band alignments of Si and unstrained Si1-xGexgrown on Si substrate; (b) A schematic of unstrained Si1-xGexfilm deposited on Si; (c) Band alignments of compressively strained Si1-xGexgrown on Si; (d) A schematic of compressively strained Si1-xGexas a result of pseudomorphic growth on Si.

III. SIMULATION RESULTS AND DISCUSSION

1. Device Simulation Results

Fig. 4(a) shows the simulated I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ curves of Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ TFETs for three x values. I$_{\mathrm{D}}$ consists of turn-on current (I$_{\mathrm{turn-on}}$), ambipolar current (I$_{\mathrm{amb}}$), and off-state leakage current (I$_{\mathrm{leak}}$). Also, as shown in Fig. 4(b), two kinds of threshold voltages (V$_{\mathrm{th}}$’s) are extracted: one for the turn-on state (V$_{\mathrm{turn-on}}$) and the other for the ambipolar state (V$_{\mathrm{amb}}$). They are defined as the V$_{\mathrm{G}}$’s where I$_{\mathrm{turn-on}}$ and I$_{\mathrm{amb}}$ exceed I$_{\mathrm{leak}}$, respectively ^[5].

From Fig. 4(a) and (b), it is observed that the {\textbar}V$_{\mathrm{amb}}${\textbar} decreases significantly with higher x value. On the contrary, V$_{\mathrm{turn-on}}$ remains almost the same even if the x value varies. It can be explained by the energy band diagrams presented in Fig. 5(a) and (b). V$_{\mathrm{turn-on}}$ is determined by the point where the lowest conduction band edge (E$_{\mathrm{c}}$) of the channel exceeds the highest valence band edge (E$_{\mathrm{v}}$) of the source ^[18]. However, as shown in Fig. 3, the ${\Delta}$E$_{\mathrm{c}}$ is almost zero regardless of the x values of Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$. Thus, V$_{\mathrm{turn-on}}$ to induce an energy overlap window between the source valence band and the channel conduction band remains almost unchanged. Meanwhile, I$_{\mathrm{turn-on}}$ is boosted owing to the smaller bandgap and effective mass, and consequently enhanced electron tunneling probability. In contrast, because the ${\Delta}$E$_{\mathrm{v}}$ increases significantly with higher x value, it requires lower {\textbar}V$_{\mathrm{amb}}${\textbar} to shift the E$_{\mathrm{v}}$ of the channel over the E$_{\mathrm{c}}$ of the drain, as can be derived from Fig. 5(b). As a result, with increasing x value, {\textbar}V$_{\mathrm{amb}}${\textbar} decreases and it increases I$_{\mathrm{amb}}$ more rapidly than the I$_{\mathrm{turn-on}}$ under the same bias conditions.

Fig. 4. (a) ID-VG characteristics of simulated Si1-xGexTFETs with parameters corresponding to unstrained Si1-xGex; (b) The change of Vth and ID (extracted at |VG| = 1.5 V) in ambipolar and turn-on states depending on the Ge mole fraction.

Fig. 5. Simulated lateral energy band diagrams of unstrained Si1-xGexTFETs that represent: (a) source-to-channel junction which controls the n-type turn-on states; (b) drain-to-channel junction which controls the p-type ambipolar states, respectively. The y-axis value is set so that the quasi electron/hole Fermi level in the source region is zero.

2. Circuit Simulation Results

In this section, we investigate the influence of the x value on the transient switching characteristics of ambipolar Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ TFETs. The simple inverter and NAND gate characteristics were simulated by HSPICE ^[19]. Our TFET compact model ^[18,20] was calibrated referring to the TCAD simulation data as shown in Fig. 6. The previous model, based on 1-D Zener tunneling only considered the I$_{\mathrm{turn-on}}$ of TFETs, neglecting the ambipolar behavior. Thus, we modified the model to operate as a unified model that simultaneously describes the turn-on and ambipolar state characteristics. Even if ambipolar FETs-based complementary-like logic gates may consist of the identical devices ^[3], for V$_{\mathrm{DD}}$ downscaling, two identical devices with different gate work functions are used. Fig. 7(a) and (b) represent the circuit schematics of ambipolar Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ TFETs-based inverter and NAND gate, respectively. There are two signal propagation paths determining the output. In the case of the pull-up part, connected from V$_{\mathrm{DD}}$ to the output node, the I$_{\mathrm{amb}}$ drives the transient response. On the contrary, in the pull-down part, linked from the output node to the ground, the I$_{\mathrm{turn-on}}$ drives the transient response.

Fig. 7(c) shows the simulated transient response of the ambipolar Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ TFET-based complementary-like inverters with increasing the x value. The tendency for propagation delay can be predicted from the relatively small increase in I$_{\mathrm{turn-on}}$ and the significant increase in I$_{\mathrm{amb}}$. The rising time decreases more abruptly than the falling time because I$_{\mathrm{amb}}$ dominates the rising time, while I$_{\mathrm{turn-on}}$ dominates the falling time. Pull-up delay decreases from 650 ns to 8 ns while pull-down delay decreases from 185 ns to 20 ns. The dynamic power consumption in the worst case increases from 0.94 nW to 2.21 nW when x increases from 0 to 0.5. The degree of decrease in delay and increase in power accompanied by higher x value is consistent with the previous study which focused on the transient performance of n-type pull-down TFETs based on Si and SiGe ^[21]. Also, in TFET inverters, voltage undershoot and overshoot occur at the output low-to-high and high-to-low transitions, respectively ^[22]. As shown in Fig. 6(b), the gate-to-drain and gate-to-source capacitance (C$_{\mathrm{GD}}$ and C$_{\mathrm{GS}}$) of TFETs in the linear region stays almost the same regardless of the x value. Therefore, the extent of overshoot and undershoot is the same for different x values. Meanwhile, C$_{\mathrm{GS}}$ in the ambipolar state increases more rapidly with a higher x value, while the behavior of C$_{\mathrm{GD}}$ in the turn-on state changes little. The reason is the same as explained in the previous section regarding the ${\Delta}$E$_{\mathrm{c}}$’s and ${\Delta}$E$_{\mathrm{v}}$’s with different x values. In the transient behavior of NAND gates as shown in Fig. 7(d), the propagation delay from low to high decreases more than the delay from high to low with increasing the x value.

Thus, to design ambipolar Si$_{\mathrm{1-x}}$Ge$_{\mathrm{x}}$ TFET-based complementary-like logic integrated circuits, the different tendency in the propagation delay related to the I$_{\mathrm{turn-on}}$ and I$_{\mathrm{amb}}$ for x variations needs to be considered for appropriate signal manipulation.

Fig. 6. (a) Transfer characteristics; (b) CGD/CGS-VG characteristics of Si1-xGexTFETs used for complementary-like logic operation. For TFET components with red lines, transient responses are driven by the Iamb. For blue lines, transient responses are driven by the Iturn-on.

Fig. 7. (a) Configuration of the ambipolar Si1-xGexTFET-based inverter; (b) NAND gates; (c), (d) their transient switching characteristics. The load capacitance is 1 fF. In the TFET symbols, the direction in which BTBT occurs mainly in the operating bias regime is indicated.

IV. CONCLUSIONS

The influence of the channel stoichiometry of SiGe TFETs on the ambipolar behavior was investigated via simulations. At the device level, it is observed that a higher Ge mole fraction enhances the carrier transports of both polarities. At the same time, it has a more significant effect on the V$_{\mathrm{th}}$ shift and on-current boosting for the hole-dominated regime than for the electron-dominated regime. Finally, when applied to complementary-like logic operations, the pull-up network becomes stronger than the pull-down network with increased x value in terms of current driving.