https://doi.org/10.5573/JSTS.2026.26.4.239

(Wongi Cho) ; (Seonghearn Lee)

An improved SPICE macro model based on BSIMSOI4 has been proposed for accurate modeling of short-channel floating-body PD-SOI MOSFETs. The kink and self-heating effects are modeled individually using empirical I-V equations. For both low-frequency and RF inductive effects, frequency-dependent empirical equations of intrinsic output capacitance and conductance are newly used to accurately model the overlapping behavior of both effects in the low-frequency region. This model shows improved Y22-parameter fitting accuracy compared to conventional models. To account for substrate loss not considered in BSIMSOI4, the substrate resistance is externally added to the model, improving S-parameter accuracy at high frequencies. The proposed RF-based extraction method allows precise modeling of overlap and junction capacitance parameters. Validation against measured S-parameters at 0.1 μm gate length up to 20 GHz confirms the accuracy of the improved model and parameter extraction across various bias conditions.

https://doi.org/10.5573/JSTS.2026.26.4.249

(Tae Young Yoon) ; (Kang Hee Lee) ; (Jun Seok Lee) ; (Mincheol Kim) ; (Yongyoon Choi) ; (Jang Hyun Kim)

The Complementary Metal Oxide Semiconductor (CMOS) inverter is a fundamental digital circuit in the semiconductor industry due to its low power consumption and high-speed performance. Especially, fully depleted silicon-on-insulator (FDSOI) devices provide significant advantages in low power consumption and process simplicity. To optimize this CMOS inverter for various environments, Technology Computer Aided Design (TCAD) simulation is utilized since multiple factors need to be considered. However, optimization of numerous factors is inefficient due to its repeatability and restricted computing resources. In this work, a novel approach to CMOS inverter optimization is proposed applying the Deep Learning (DL) algorithm which consists of neural network for an efficiency. To optimize the DL model for CMOS inverter data, we iteratively refined the model based on metrics such as Mean Squared Error (MSE), Mean Absolute Error (MAE), etc. As a result, we obtain a model with a low error rate while avoiding overfitting. Using this optimized DL model, we perform the optimization process and identify an optimal point where delay time is improved by 69.4% and power loss by 71.4% compared to the reference device.

https://doi.org/10.5573/JSTS.2026.26.4.257

(Hai Dang Ngo) ; (Bao Quan Tran) ; (Khac Binh Nguyen) ; (Hoai Phuong Pham) ; (Thi Kim Hang Pham)

In this work, radio frequency reactive magnetron sputtering was used to grow MgxZn1?xO thin films on glass substrates as a function of substrate temperature. The effect of substrate temperature on crystal structure, elemental composition, and optical characteristics was examined by X-ray diffraction, energy-dispersive X-ray spectroscopy, and UV-Vis transmittance spectroscopy. All MgZnO thin films had a preferential orientation along the (002) plane, signifying robust c-axis growth perpendicular to the substrate and affirming the hexagonal wurtzite structure typical of ZnO. The crystallite size ranged from 7.97 to 12.98 nm, with the maximum value achieved at 250 ?C. The elements Zn, Mg, and O were identified, and the Mg composition was determined to be x = 0.33 in MgxZn1?xO. Thin films exhibited significant optical transparency, with an average transmittance of around 95% within the visible spectrum. The optical band gap, ascertained by Tauc plots, exhibited a slight increase from 3.80 to 3.86 eV with rising temperature. The refractive index, extracted from the Swanepoel method, varied from 2.15 to 2.58. These results underscore the promise of MgZnO thin films for prospective applications in optoelectronic and UV-transparent devices.

https://doi.org/10.5573/JSTS.2026.26.4.265

(Balaramamurty Sannidhi) ; (G. V. K. Sharma)

A novel complementary-to-absolute-temperature (CTAT) generator-based voltage reference circuit is proposed. The design features a resistor-less, ultra-low-power, sub-1 V MOSFET-only sub-threshold voltage reference compatible with digital CMOS processes, making it suitable for low-power and compact applications. The proposed circuit achieves a reference voltage of 0.581 V and utilizes highly linear proportional-to-absolute-temperature (PTAT) and CTAT generators to ensure a low temperature coefficient of 5.5 ppm/?C across a wide temperature range from ?50?C to 150?C. The circuit’s analytical behavior is modeled, and extensive post-layout analog simulations in a 0.18-μm CMOS process validate the design performance. It demonstrates excellent line sensitivity of 0.1%/V across a supply voltage range of 0.8 to 3 V and achieves a power supply ripple rejection (PSRR) of ?53 dB at 100 Hz. The circuit occupies an area of only 0.005315 mm2 and consumes 4.5 nW at 27?C. The compact and efficient design addresses the challenges of achieving stability, scalability, and low power in modern CMOS-based systems.

https://doi.org/10.5573/JSTS.2026.26.4.272

(Won Suk Koh) ; (Jin Park) ; (Gang San Yun) ; (Soo Bean Song) ; (Kyeong Min Lim) ; (Sang Ho Lee) ; (Young Jun Yoon) ; (In Man Kang)

This study proposed and analyzed a capacitorless one-transistor dynamic random-access memory (1TDRAM) based on a gate-all-around junctionless field effect transistor (GAA-JLFET) featuring a vertically stacked storage layer and an underlapped gate structure. The device incorporated a 2 nm Si0.8Ge0.2 storage region with a higher valence band offset than silicon (Si), enabling stronger hole confinement and improved storage potential. A negative hold bias of -0.5 V was applied to extend hole retention and suppress diffusion during the program operation. At 358 K, the design achieved a sensing margin (SM) of 1.13 μA/μm and a retention time (RT) of 50.7 ms, which did not satisfy the International Roadmap for Devices and Systems (IRDS) requirement of 64 ms. Since the baseline design did not meet the target, the retention loss was attributed to recombination concentrated near the source-side Si0.8Ge0.2 region. By partially removing the Si0.8Ge0.2 layer adjacent to the source to suppress the recombination rate in that area, the SM and RT were improved to 1.24 μA/μm and 106.53 ms, respectively.

https://doi.org/10.5573/JSTS.2026.26.4.283

(Yoon Tae Jeong) ; (Jae SeungWoo) ; (Jin Ho Chang) ; (Hye Sun Sung) ; (Hyo Jung Kim) ; (Seung Bo Shim) ; (Woo Young Choi)

A novel hot-carrier lifetime prediction method is proposed for long-channel p-channel MOSFETs in the subthreshold region, which can be used for various driving transistor applications: organic light-emitting diode on silicon (OLEDoS), DC/DC converters, power inverters and LEDs. Owing to the extremely low subthreshold current of p-channel MOSFETs, it is challenging to detect hot-carrier-induced degradation (HCD) for > 10,000-s stress time, which makes lifetime prediction difficult. In this work, both experimental and simulation data show that the secondary hot electron energy which is the primary degradation factor of p-channel MOSFETs is proportional to the gate (VG) and drain (VD) voltage difference (VGD). Consequently, by simultaneously increasing VG and VD while preserving the VGD, the HCD lifetime prediction of p-channel MOSFETs can be successfully accelerated in the subthreshold region. For example, the HCD lifetime of long-channel p-channel MOSFETs is estimated to be 2.90×1012 s at VG = ?0.7 V referring to the experimental data measured at VG = ?1.5 V.

https://doi.org/10.5573/JSTS.2026.26.4.292

(Dohyun Kim) ; (Wonbo Shim)

Hybrid bonding-based 3D NAND Flash memory architectures suffer from severe threshold voltage (Vth) distribution broadening. This issue arises from vertical thermal gradients induced by the underlying peripheral circuits, which can compromise the read margin and endurance. In this work, we propose a voltage control scheme to overcome these challenges by incorporating a position-dependent gradient bias according to the temperature during the erase operation. Additionally, it employs a temperature-dependent adaptive pass voltage (Vpass) adjustment during the read operation. This approach mitigates temperature-dependent channel potential variations, thereby widening the narrowed read margin and improving cycling endurance. Through TCAD simulations, we analyzed the electrical characteristics of both body contact spacer (BCS) and channel-hole sidewall ONO butting (CSOB) structures. The Vth shift following the erase operation was suppressed from 200 mV to 10 mV for the BCS structure and from 850 mV to 10 mV for the CSOB structure. Verification under both matched and mismatched thermal scenarios demonstrated significant improvements. Consequently, we effectively narrowed the distribution width and enhanced the long-term cycling endurance of high-bit-density 3D NAND Flash memories.