https://doi.org/10.5573/JSTS.2026.26.3.181

(Siyeol Lee) ; (Dasom Ahn) ; (Sung Hun Jin) ; (Taehui Na)

To address the bottleneck caused by the memory wall in conventional computing systems, in-memory computing (IMC) has gained significant research interest. While the digital approach to IMC can achieve high accuracy, its energy efficiency is often lower than that of analog IMC approaches. To address this limitation, the Ternary-output Binary Neural Network-based IMC (ToBNN-IMC) has gained attention. ToBNN-IMC can achieve both high accuracy and energy efficiency through its digital nature and the use of a zero-skipping technique. However, ToBNN-IMC has been experienced only with STT-MRAM memory macro. Moreover, its accumulating strategy, which counts multiplication results using a counter with a fixed bit-width, can suffer from degraded accuracy when the number of multiply-accumulate (MAC) operations exceeds the counter’s range. To overcome this issue, the proposed digital-memory hybrid counter-based SRAM IMC (hybrid SRAM-IMC) employs a counter design referred to as the scalable exponent counter, which enables accurate accumulation and direct extraction of neuron activation regardless of the number of MAC operations. By implementing this design, the hybrid SRAM-IMC achieved 96.58% inference accuracy on the MNIST dataset, 88.64% on the CIFAR-10 dataset, and 94.00% on the SVHN dataset, demonstrating accurate MAC operation without any accuracy loss, regardless of the number of accumulations.

https://doi.org/10.5573/JSTS.2026.26.3.192

(Shengcheng Liu) ; (Jiawei Yuan) ; (Qian Liu) ; (Zhibing Yan) ; (Tianxi Yang) ; (Jie Sun) ; (Qun Yan)

Micro light-emitting-diodes (Micro-LEDs), as core components of next-generation displays, offer high brightness, low power consumption, long lifespan, and fast response. However, the commercial development of red and green Micro-LEDs is hindered by low quantum efficiency and immature mass transfer technology. Meanwhile, although organic light-emitting diodes (OLEDs) have achieved stable commercial application with red and green phosphorescent materials, blue phosphorescent OLEDs still suffer from insufficient luminous efficiency and short device lifetime. To overcome these limitations, this study proposes a novel full-color display design by integrating blue Micro-LEDs with red and green OLEDs in a single passive-driven matrix, eliminating the need for mass transfer. Passive matrix devices with two different mesa sizes were fabricated on a 4-inch blue epitaxial wafer. A series-parallel sub-pixel structure was adopted, which effectively reduces electrode wiring complexity while significantly improving pixel density. In this study, we conducted photoelectric tests on the two different mesa - sized blue Micro-LEDs and red and green OLEDs. The turn-on voltage of the blue Micro-LEDs was 2.7 V, while that of the red and green OLEDs was 3.0 V?values close enough to allow simultaneous illumination under the same driving circuit. At a voltage of 4.5 V, the luminance of the 20×70 μm2 blue Micro-LED reached 3.08×104 cd/m2 , while that of the 40 × 90 μm2 blue Micro-LED achieved 3.69 × 104 cd/m2 . At 5 V, the luminance of the 50×70 μm2 green OLED reached 87.37 cd/m2 , the 70×90 μm2 green OLED reached 100.13 cd/m2 , the 50×70 μm2 red OLED reached 18 cd/m2 , and the 70×90 μm2 red OLED reached 28.1 cd/m2 .

https://doi.org/10.5573/JSTS.2026.26.3.203

(Daeman Seo) ; (Sungman Lee) ; (Seungjae Baik) ; (In-Ho Lee)

Particle contamination during wafer processing posed a critical challenge in semiconductor manufacturing, as it directly affected device yield and reliability. This study investigates the mechanisms of particle generation in the polycrystalline silicon (Poly-Si) deposition process using low pressure chemical vapor deposition (LPCVD) within a furnace-type system. Using energy dispersive X-ray spectroscopy (EDX) and scanning electron microscopy (SEM), the analysis identifies wafer warpage?caused by thermal stress differentials?as a key contributor to particle formation. To address this issue, the study develops a method that enhances heat transfer uniformity between the wafer center and edge, thereby reducing film stress and suppressing warpage. Experimental results demonstrate the effectiveness and reliability of the proposed approach. Production results show an improvement of approximately 6.7% in particle counts. When applied to more than 10,000 wafers in mass production, the optimized deposition method achieves a significant reduction in particle generation, leading to improved process yield and reliability.

https://doi.org/10.5573/JSTS.2026.26.3.212

(Weizheng Wang) ; (Xiang Zhu) ; (Tieqiao Liu)

Logic locking technology effectively combats piracy and reverse engineering threats in integrated circuits. The advent of the SAT attack fundamentally altered the landscape of traditional logic locking techniques. Subsequently developed countermeasures primarily focused on resisting SAT attacks. However, most logic locking schemes face a critical trade-off between SAT attack resilience and output corruptibility. Techniques exhibiting high SAT resistance typically fail to achieve significant corruption at the circuit outputs and often require combination with other schemes. Unfortunately, such composite approaches are vulnerable to attacks like AppSAT. While some locking techniques have managed to increase output corruptibility, the achieved levels remain relatively low. This paper proposes Maximum Output Corruption Anti-SAT Logic Locking (MOCASLL). Unlike other designs aimed at increasing corruption, MOCASLL guarantees near-maximal resistance to SAT attacks (requiring 2n ? 1 iterations) while simultaneously ensuring the highest possible output corruptibility, approaching 50%. Furthermore, MOCASLL demonstrates resilience against removal attacks and maintains low hardware overhead.

https://doi.org/10.5573/JSTS.2026.26.3.222

(Kyuho Lee)

An energy-efficient keypoint extraction processor is proposed for real-time LiDAR-based SLAM. The keypoints are extracted from sorted curvature map, that sorting process is the main bottleneck occupying 85.9% of KE latency. The extracted keypoints occupy 7.9% of total input points, that sorting process is operated with huge redundant data. To address this, near-keypoint removal and candidate filtering unit are proposed to exclude 92.1% of redundant data which is not extracted as keypoints removing 42.8-63.0% of data, resulting in 19.5-43.0% of latency reduction. Additionally, input points vary 31.9× in channel-wise and 5.1× in frame-wise, causing huge workload variance. Reconfigurable radix sorting is proposed, that 16 radix-based sorting with 0.34 MB/frame low-memory bandwidth is operated with low workload. With a high workload, 2 radix-based sorting can achieve 28.1 μs of low processing time operating with high speed. The proposed processor is fabricated in 28 nm CMOS technology, occupying 0.57 mm2 , with 7.26 mW power consumption and 675.2 nJ/frame of efficiency which is 998661× higher than the previous CPU.

https://doi.org/10.5573/JSTS.2026.26.3.228

(Hyunji Kim) ; (Ji-Hoon Kim)

Sparse matrix-vector multiplication (SpMV) is a memory-bound kernel widely used in scientific computing, machine learning, and graph analytics, where bandwidth utilization (BU) serves as a key performance metric for hardware accelerators. In our prior work, we presented a DRAM bandwidth-scalable SpMV accelerator whose processing element (PE) line count scales with DRAM bandwidth, combined with offline pre-processing to eliminate bank conflicts and data dependencies, achieving an average BU of 89% of the theoretical maximum. However, its column-index-based equal partitioning can cause significant PE line load imbalance when nonzero elements are unevenly distributed across columns, leaving faster PE lines idle and degrading BU?an effect that intensifies as PE line count increases with higher off-chip bandwidth. In this paper, we analyze the relationship between column-wise nonzero distribution and PE line imbalance using 29 SuiteSparse benchmark matrices and propose a nonzero-aware partitioning strategy that assigns column ranges based on the actual number of nonzero elements to equalize workloads across PE lines. While the offline pre-processing in our prior work focused on conflict-free data rearrangement, the proposed method targets the preceding partitioning stage, requiring no modification to the on-chip accelerator hardware. Cycle-accurate simulation on 29 matrices across three configurations (2, 4, and 8 PE lines) shows average BU improvements of 17.2%, 65.4%, and 113.7% for 2, 4, and 8 PE line configurations, respectively, with zero degradation across all matrices and configurations, confirming that the method preserves the bandwidth scalability of the baseline accelerator.

https://doi.org/10.5573/JSTS.2026.26.3.235

(Jun-Cheol Lee) ; (Joo-Hyung Chae)

This letter introduces a time-domain receiver (RX) for next-generation low-power memory interfaces. To address the limitations of VSS-terminated signaling, the RX adopts VTT-terminated signaling, which offers improved performance in terms of power consumption, pre-emphasis applicability, and simultaneous switching output noise tolerance. Furthermore, we employ a track-and-hold circuit to prevent voltage-to-time converter gain reduction caused by data transitions. The prototype RX was fabricated in a 65-nm CMOS process and occupied an area of 0.0058 mm2 . The RX achieved a data rate of 14 Gb/s at a supply voltage of 0.9 V with an insertion loss of -11.8 dB at 7 GHz, and consumed 1.61 mW, resulting in an energy efficiency of 0.115 pJ/bit.