https://doi.org/10.5573/JSTS.2026.26.5.299

(Paul Jeremiah) ; (Inn-Yeal Oh)

Accurate cell-voltage monitoring in battery management systems (BMS) requires a reference voltage whose temperature drift is well below the 1 mV measurement target. This paper presents a PMOS-only stacked, triode-region voltage reference architecture that combines complementary-to-absolute-temperature (CTAT) current behavior in the weak-triode region with proportional-to-absolute-temperature (PTAT) current behavior in the deeptriode region to achieve a balanced temperature slope. The PMOS gate width was optimized to 50 μm in 180-nm CMOS to balance the CTAT/PTAT components. In addition, a body-effect (VSB) bias generator is employed to adjust the effective PMOS threshold voltage and further flatten the composite temperature characteristics. The reference is programmable trimmed by a two-stage coarse-fine decoder to realize a 3.2-4.2 V output range with 1 mV resolution, targeting ?Σ ADC-based BMS front ends. The proposed design achieved an ultra-low temperature variation of 0.3 mV from -20?C to 100?C, corresponding to a temperature coefficient of 0.61 ppm/?C, with an active area of 0.0038 mm2 .

https://doi.org/10.5573/JSTS.2026.26.5.307

(Hyunki Park) ; (Jaemyung Lim)

This paper presents a high-resolution time-to-digital converter (TDC) for accurate pulse-width measurement of impulse radio pulse width modulation (IR-PWM) signals in wireless data acquisition systems. To improve timing resolution, the proposed TDC replaces conventional inverters with buffers in each delay stage, achieving a resolution of 2.94 ps and supporting an 8-bit dynamic range. An on-chip PWM generator is integrated to evaluate the TDC performance, generating pulse widths ranging from 400 ps to 830 ps. Fabricated in a 28-nm CMOS process, the TDC and PWM generator occupy areas of 14.3 μm × 405 μm and 14.3 μm × 6.3 μm, respectively. Operating at a 1 V supply, the TDC consumes 970 μW of power. Linearity tests show a differential nonlinearity (DNL) within ±0.55 LSB and an integral nonlinearity (INL) within ±1.5 LSB, confirming the accuracy of the proposed system.

https://doi.org/10.5573/JSTS.2026.26.5.313

(Jincan Zhang) ; (Jiahao Yao) ; (Wenshuai Liu) ; (Jingyu Chang) ; (KexinWang)

A method for extracting intrinsic parameters by combining the Principal Component Analysis (PCA) algorithm with the Osprey Optimization Algorithm (OOA) is proposed in this paper. Traditional methods for extracting intrinsic parameters from Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) face challenges, such as long S-parameter modeling times and low accuracy. To improve model accuracy, the OOA algorithm can be used to optimize the intrinsic parameters. However, the OOA algorithm has drawbacks, such as a tendency to fall into local optima and high sensitivity to parameters. Additionally, it does not account for correlations between intrinsic parameters, which limits improvements in model accuracy. To further enhance the model’s precision, PCA is applied in this paper to strengthen the correlation between intrinsic parameters. The PCA-processed intrinsic parameters are then combined with the OOA algorithm for extraction. Experimental results show that over the wide frequency range of 0.5?20.5 GHz, the PCA-OOA algorithm significantly improves S-parameter modeling accuracy compared to traditional extraction techniques, offering a new approach for efficient and accurate modeling of GaN HEMT devices.

https://doi.org/10.5573/JSTS.2026.26.5.327

(Jonghoon Park) ; (Dongyong Choi) ; (Jungmin Kwon) ; (Kabseok Ko) ; (Kuduck Kwon) ; (In-Chul Hwang) ; (Seungyoung Park)

Minimizing integrated phase noise (IPN) in RF phase-locked loops (PLLs) is critical to spectral purity and system-level performance, yet post-fabrication tuning relies on expensive measurements over discrete trimming codes, making exhaustive search impractical. Therefore, sample-efficient optimization is essential, especially when instrumentation time is limited and the configuration space is large. This study investigates batch Bayesian optimization (BO) with batch expected improvement for minimizing IPN of RF PLLs under discrete trimming codes and expensive measurements. Although parallel test resources typically drive batch BO, we considered a singledevice-under-test setup in which q candidates were queued and sequentially measured. We evaluated performance as a function of the total number of physical measurements B, comparing it against sequential BO and genetic algorithms across three PLL boards. For small B, a moderate batch size accelerated IPN reduction and improved tail behavior. At larger B, the mean performance of batch BO was comparable to that of sequential BO. However, batch BO retained a tail-performance advantage on certain boards. Additionally, within batch BO, we observed a non-monotonic effect of the batch size q. Specifically, moderate batch sizes improved early progress, whereas excessively large q degraded performance due to selecting all batch candidates simultaneously without using intermediate measurement feedback. These results suggest that appropriate batch-size selection can reduce the number of measurements required to achieve a target IPN, making batch BO particularly attractive under constrained measurement budgets.

https://doi.org/10.5573/JSTS.2026.26.5.340

(Hyeon Cheol Kim) ; (Sameer Pokhrel) ; (V. Janardhanam) ; (Chel-Jong Choi) ; (Kyu Hwan Shim)

We have systematically investigated the effect of the variation in the doping concentration and thickness of the Cu2O layer on the electrical characteristics of the p-type Cu2O/n-type Ga2O3 heterojunction p-n diode. In particular, the effect of the doping concentration and thickness of Cu2O was explored in order to enhance the breakdown voltage of the p-type Cu2O/n-type Ga2O3 heterojunction p-n diode. The on-resistance of the device was noted to decrease from 41.2 MΩ·cm2 to 0.815 mΩ·cm2 with increasing electron affinity of the Cu2O layer. The breakdown voltage of the device increased with increasing doping concentration and increase in thickness of the Cu2O layer until the respective values reached to 1 × 1018 cm?3 and 200 nm with the breakdown voltage of the p-n diode reaching 1500 V. The increase in breakdown voltage of the p-n diode with thickness of Cu2O layer is attributed to the fact that a thicker layer could accommodate a wider depletion region. While the increase in breakdown voltage with doping concentration of p-type Cu2O is due to widening of the depletion width in the drift layer. An electric field distribution under the anode edges for the p-type Cu2O/n-type Ga2O3 heterojunction p-n diode has been presented and discussed in detail through technology computer aided design (TCAD) simulation. The results of this work provide a vital insight for the design and performance enhancement of the next-generation Ga2O3-based high-power devices.

https://doi.org/10.5573/JSTS.2026.26.5.351

(B. Priya) ; (J. M. Nandhini) ; (S. Gurusubramani) ; (Gnanasekaran Thangavel)

The application of conventional tin dioxide (SnO2) gas sensors is inadequate because of their high operating temperature, poor selectivity, and low gas response. Nanomaterials enhance gas-sensing properties through surface effects, nanoscale dimensions, and quantum-size effects. The development of SnO2 nanomaterial-based sensors through nanotechnology substantially improves gas sensing performance. The increasing concentration of greenhouse gases significantly contributes to climate change and global warming. Conventional gas sensing strategies face challenges in terms of selectivity, sensitivity, and adaptability under unpredictable environmental situations. To address these concerns, this article proposes a hybrid approach that combines SnO2 nanostructure-based semiconductor gas sensors with a reinforcement learning (RL) model to achieve accurate detection and greenhouse gas categorization. SnO2 nanostructure provides efficient electron transport, larger surface area, and enhanced adsorption properties, while the RL model enables adaptive and intelligent gas categorization. Experimental results show that SnO2 nanostructure combined with the RL algorithm achieves faster response time, improves gas-sensing performance, and provides more reliable discrimination for detecting greenhouse gas.

https://doi.org/10.5573/JSTS.2026.26.5.364

(Young-Jun Yu) ; (Jihoon An) ; (Ik-Jae Kim) ; (Jaehyun Ko) ; (Byungsub Kim) ; (Jang-Sik Lee) ; (Dong-Woo Jee)

Compute-in-Memory (CIM) has emerged as a promising solution for high-speed and energy-efficient artificial intelligence computation. Among various memory technologies, FeFET devices provide several advantages such as multi-level operation, high-density integration, and CMOS compatibility for CIM applications. This study presents a scalable 3D FeNAND array interface circuit for CIM systems, integrating high-voltage (HV) driver, source-line (SL) driver, and word-line (WL) MUX, that supports both high-voltage driving of memory devices for a wide memory window and reliable interfacing with low-voltage CMOS circuits. The HV driver, SL driver, and WL MUX are designed to have wide-range high-voltage generation with digital controllability, ultra-low memory current sensing(< 100 nA), and fast WL voltage switching (< 100 ns), respectively. The proposed chip was fabricated in a 180 nm BCD process and experimentally verified to support the target 8×3 3D FeNAND array by generating standby, erase, program, and read signals for CIM operation

https://doi.org/10.5573/JSTS.2026.26.5.374

(Younghoo Ro) ; (Jun Lee) ; (Eungi Hwang) ; (Garam Kim)

In this study, we propose an enhanced 1T-DRAM-based synaptic device structure aimed at improving conductance characteristics and linearity during potentiation and depression. While conventional 1T-DRAM based synaptic devices using a uniform SiGe body suffer from degraded linearity due to rapid hole saturation across the entire body region, our approach introduces a degraded SiGe body structure in which the body is divided into three sections with gradually decreasing Ge mole fractions (0.3, 0.2, and 0.1) from the source to the drain side. This gradient design enables more effective hole storage during potentiation and depression compared to a uniform SiGe body, alleviating abrupt saturation and thereby enhancing linearity. The proposed structure is evaluated in a multilayer perceptron (MLP) simulation using NeuroSim, demonstrating increased classification accuracy with respect to training epochs.

https://doi.org/10.5573/JSTS.2026.26.5.384

(Yoonsang Lee) ; (Hyunsu Jang) ; (Myeongju Park) ; (Jongchan An) ; (Junyoung Song)

In this study, a switched-capacitor peaking (SCP) feed-forward equalizer (FFE) is proposed to compensate for attenuation and distortion caused by channel loss in high-speed memory interfaces. The proposed SCP achieves both signal integrity enhancement and signal bandwidth preservation by implementing pre-emphasis while minimizing I/O capacitance (CIO). Furthermore, by pre-distorting according to the emphasis coefficient, the overhead of the output driver is minimized. The proposed SCP transmitter, implemented in a 28-nm CMOS process, compensates for ?9.2 dB of channel loss at 8 GHz, achieving an energy efficiency of 0.129 pJ/b/dB with vertical and horizontal eye margins of 61 mV and 0.65 UI, respectively

https://doi.org/10.5573/JSTS.2026.26.5.390

(Tae Young Yoon) ; (Kang Hee Lee) ; (Jun Seok Lee) ; (Mincheol Kim) ; (Yongyoon Choi) ; (Seung Kyu Kim) ; (Ji-Hoon Kang) ; (Kee-Won Kwon)

A signal integrity and routing density analysis of a chessboard patterned interconnect (CPI) structure for Si bridge-based die-to-die interconnects is presented, targeting compliance with the Universal Chiplet Interconnect express (UCIe) standard. The CPI structure is compared against conventional fully shielded (FS) S1G1 and SnG1 configurations through full-wave electromagnetic and time-domain simulations. Key electrical transmission performance metrics include S-parameters, power-sum crosstalk (PSNEXT and PSFEXT) and voltage transfer function (VTF) loss and crosstalk?used to evaluate the cumulative impact of multiple aggressor signals?as well as eye diagram and bit error rate (BER). Results show that CPI achieves twice the routing density of FS S1G1 while satisfying overall UCIe specifications, except VTF crosstalk at high-speed operation due to diagonal aggressors. Nevertheless, CPI outperforms FS SnG1 configurations, which fail to meet crosstalk specifications owing to insufficient shielding. To improve high-speed signal integrity of the CPI, two mitigation strategies are explored: widening the ground line and selectively converting diagonal signal lines into ground. These approaches effectively reduce crosstalk while maintaining CPI’s density advantage. The findings demonstrate that the CPI configuration is a promising interconnect structure for advanced packaging, offering both high throughput and design flexibility

https://doi.org/10.5573/JSTS.2026.26.5.399

(Jin Ho Chang) ; (Seon Ho Lee) ; (Jaemin Yeom) ; (Jae Hyun Nam) ; (Kyung Moon Kim) ; (Jisun Baek) ; (Da Eun Yang) ; (Suk-Kang Sung) ; (Jun Hyoung Kim) ; (Byung Chul Lee) ; (Woo Young Choi)

This work investigates the impact of channel hole geometry and fabrication-induced device variations on 3D NAND flash memory using three-dimensional technology computer-aided design (TCAD) simulations. The channel hole diameter (dhole) is varied over a practical range, tapered and elliptic profiles are introduced to emulate high-aspect-ratio etch distortion, and oxide-nitride-oxide (ONO) thickness fluctuation is applied to reflect deposition non-idealities. The study focuses on the programmed threshold voltage (Vth), subthreshold swing (SS), and bit-line (BL) current (IBL) of each WL and also includes the effect of read temperature in the typical operating range. The results indicate that reducing dhole increases the program efficiency while decreasing IBL. Regarding process variations, both increased ellipticity and ONO thickness were found to degrade the programmed Vth. However, while IBL increases notably with ellipticity, it exhibits a relatively weak dependence on ONO thickness. Furthermore, elevated read temperatures consistently reduce the apparent Vth and IBL, thereby tightening the sensing margin for multi-level operation. These findings elucidate the distinct impacts of geometric scaling on device variability and provide useful design guidelines for high-density memory architectures.

https://doi.org/10.5573/JSTS.2026.26.5.407

(Dongwook Kim) ; (Kyuho Jason Lee)

Keyword spotting (KWS) is an essential technology for realizing always-on voice interfaces in edge devices, demanding extremely low-energy operation. Computing-in-Memory (CIM) architectures are promising for energy-efficient neural network processing by eliminating frequent external memory access. However, previous CIM-based KWS processors still suffer from low utilization in depthwise convolution (DWCONV) and significant energy consumption in analog-to-digital converters (ADCs). This paper presents an eDRAM-based CIM processor that achieves high integration density and ultra-low-energy end-to-end KWS operation through three key innovations. First, a frequency-selective stride convolution (FSSC) algorithm reduces the length of the raw audio input by 99.22%, thereby minimizing memory usage and computational complexity. Second, a multi-stationary CIM architecture maximizes hardware utilization in the DWCONV layer and reduces MAC energy by 95.26% by decreasing wordline driving activity. Third, a scalable-precision ADC optimizes capacitive digital-to-analog converter (CAP-DAC) switching energy according to the output range, achieving up to 75.71% lower conversion energy. As a result, the proposed processor achieves 95.1% accuracy on the 10-keyword Google Speech Commands dataset, with a macro-level energy efficiency of 34.8 TOPS/W and a system-level energy efficiency of 21.6 TOPS/W, consuming 0.62 μJ per decision

https://doi.org/10.5573/JSTS.2026.26.5.415

(Youngsoo Choi) ; (Minsik Yoon) ; (Dongmin Han) ; (Donghoon Kang) ; (Hoonroe Lee) ; (Hyunjo Hwang) ; (Jehyun Chun) ; (Sangbum Kim)

Analog in-memory computing (AIMC) offers a promising route to overcome the von Neumann bottleneck, but per-layer analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) remain a major overhead, particularly in vertical 3D structures where converter circuitry is required at each stacked layer. This work proposes a fully analog EqProp framework in which phase-change memory (PCM) devices serve as resistive synapses and Ovonic Threshold Switch (OTS) devices serve as non-linear neurons within a common vertical 3D stack, thereby eliminating layer-wise ADC/DAC interfaces. To validate this concept, vertical 3D PCM and OTS devices were fabricated and electrically characterized. The fabricated PCM demonstrates stable switching with an on/off ratio exceeding two orders of magnitude across all four layers and multilevel conductance modulation suitable for analog weight representation, with drift coefficients consistent with previously reported GST values. The OTS device achieves enhanced subthreshold non-linearity through intentional electroforming while preserving threshold switching. Incorporating the measured device characteristics into a device-aware simulation, XOR experiments confirm the feasibility of the 3D PCM-OTS architecture for the analog EqProp framework. For MNIST classification based on PCM synaptic characteristics, the fabricated PCM ensures sufficient accuracy. Furthermore, inference analysis under multiplicative conductance noise and resistance drift demonstrates that the EqProp framework maintains limited accuracy degradation under PCM synaptic non-idealities. A first-order architectural estimate shows comparable analog-core efficiency and highlights the potential system-level benefit of eliminating intermediate ADC/DAC conversions. Overall, this work suggests that vertical 3D PCM-OTS co-integration combined with the EqProp framework is a promising pathway toward fully analog AIMC without ADC/DAC overhead.