https://doi.org/10.5573/JSTS.2026.26.1.1

(Seo Yong Chi) ; (Jong Wan Park) ; (Hi-Deok Lee) ; (Wan-Gyu Lee)

To overcome the main obstacle to the wide spread use of micro-organic light-emitting diode (OLED) on Si and solve device stability, imaging uniformity, and yield, much efforts have been aimed at utilizing dual-gate structure for controlling the threshold voltage of thin film transistor (TFT). However, it is still required that standard display process or its compatible process should be setup for manufacturing of ultra high-resolution display (> 3500 ppi) of extended reality (XR), augmented reality (AR), virtual reality (VR) headset to follow the continued expansion of the market and to keep device properties. In this study, we present one of the main process parameters affecting the final electrical stability of bottom gated TFT with dual gate structure in the given process sequences existing on the sub-micron complementary metal oxide semiconductor (CMOS) technologies. The measured results demonstrate that N2 anneal (400?C, 30 min) process after amorphous indium gallium zinc oxide (a-IGZO) deposition caused the Id-Vg characteristics of IGZO TFT with Al2O3 as a bottom-gate dielectric material to be much better improvement (1×102 times) from the 5×10?8 A to 5×10?10 A at the voltage range of 0-0.5 Vg (off state), especially the characteristics of on-off transfer curve affected on the whole for the PE-oxide gate dielectric material. Secondary ion mass spectrometry (SIMS) was used to correlate the changes in gate dielectric material with the changes in electrical behavior.

https://doi.org/10.5573/JSTS.2026.26.1.8

(Sang Woo Park) ; (Jongmin Lee) ; (Jang Hyun Kim)

This study proposes a silicon nitride (Si3N4) sidewall structure for Gallium Nitride (GaN) high electron mobility transistors (HEMTs). The proposed structure effectively mitigates electric field (e-field) crowding at the gate-to-drain edge, a critical issue that leads to increased gate leakage and limited breakdown voltage (BV). Conventional GaN HEMTs suffer from severe e-field concentration, which requires effective mitigation strategies beyond conventional field plate (FP) that introduce undesirable parasitic capacitances. Our proposed sidewall structure effectively reshapes the gate edge profile, leading to a distribution of the e-field and improved device performance without requiring additional FP. The sidewall structure demonstrated a 34.76% reduction in peak e-field (from 20.13 MV/cm to 13.13 MV/cm) at the gate-drain edge compared to the conventional structure through TCAD simulations. This effective field mitigation resulted in a notable 8.8% enhancement in BV, increasing from 373 V to 406 V, and effectively suppressed gate leakage current near the BV. These results demonstrate that gate-edge sidewall engineering effectively alleviates e-field crowding, leading to improved breakdown performance and enhanced reliability in GaN HEMTs.

https://doi.org/10.5573/JSTS.2026.26.1.16

(Kiyoung Jang) ; (Junseok Heo)

Selective etching of GaN over AlGaN is a critical process step in GaN-based high electron mobility transistor (HEMT) fabrication, where precise removal of GaN is required without damaging the thin AlGaN barrier. In this study, we developed a high-selectivity, low-damage etching process using a customized BCl3/SF6 inductively coupled plasma reactive ion etching (ICP-RIE) system. Specifically, a 27.12 MHz helical resonance ICP source was utilized to generate high-density radicals and maximize gas dissociation efficiency, while the substrate temperature was precisely controlled using an external oil-circulating bath. The effects of gas composition and substrate temperature on etch rates, selectivity, and surface properties were systematically investigated. By optimizing the gas ratio to 30% SF6, a record-high GaN-over-AlGaN selectivity of 78:1 was obtained while maintaining a fast GaN etch rate. Temperature-dependent studies revealed that Al-F passivation was stable at low temperatures, whereas it degraded above 40 ?C, resulting in a significant decrease in selectivity. Although low temperatures enhanced passivation, they also promoted AlCl3 residue oxidation, resulting in unintended surface roughening. At an intermediate temperature of ∼30 ?C, the etched surface exhibited the best overall characteristics, including smooth morphology, stable chemical states, and minimized leakage current. These results demonstrate that selective, high-throughput, and low-damage GaN etching can be realized by combining optimized BCl3/SF6 chemistry with precise substrate temperature control and high-frequency ICP operation.

https://doi.org/10.5573/JSTS.2026.26.1.24

(Seong Kyum Kim) ; (Seul Ki Hong)

In order to compensate for the trade-off relationship between the dielectric’s bandgap and its dielectric constant, a triple-layer dielectric structure composed of high-k dielectrics including TiO2 was simulated. It was verified that an optimal balance between leakage current and device performance could be found by using a MOS capacitor structure with the multiple dielectric layers. Additionally, drain current analysis using a MOSFET structure confirmed that this approach can enhance electrical properties compared to using a single layer dielectric. This study suggests a process method that offers more options for satisfying device performance requirements and indicates its potential for application in various fields.

https://doi.org/10.5573/JSTS.2026.26.1.29

(Donghyun Uhm) ; (Kwanwoo Kim) ; (Hojun Kim) ; (Himchan Park) ; (Jun-Hyeok Yang) ; (Jaemyung Lim)

In this article, we present a proportional-to-absolute-temperature (PTAT) current generator that employs only MOSFETs, without the use of resistors or bipolar junction transistors (BJTs). Traditional PTAT current generators are based on the voltage difference between the base-emitter junctions of two BJTs. However, the fabrication of BJTs is increasingly limited in advanced process nodes due to their large area overhead and poor scalability. Conventional MOSFET-only designs, often rely on large resistors or suffer from high line sensitivity and poor linearity due to the channel length modulation effect. The proposed PTAT current generator utilizes two self-cascode structures, each operating in weak and moderate inversion. To enhance line sensitivity, the design incorporates a regulated cascode configuration that suppresses the channel length modulation effect. The sizes of the transistors are determined using the ACM model. In addition, by utilizing only a single type of MOSFET, the design could improve reliability against process variations. Consequently, the proposed design achieves high linearity with an R 2 value exceeding 0.9959 and exhibits line sensitivity below 0.25%/V.

https://doi.org/10.5573/JSTS.2026.26.1.36

(Jeonghun Lee) ; (Sanghyun Lim) ; (Seongjo Youn) ; (Jaehee You)

Methodologies to reduce LUT ROM amount are proposed using input pixel partitioning. To minimize the amount of error in the LUT, a scale factor is used to correct the LUT output values for the partitioned inputs, based on the input values. The dynamic range of lower bit group computation is optimized according to the step size of the upper partitioned bit group computation by the scale factor. A LUT computation and hardware design methodologies are presented utilizing image memory compression. 23.4% of the LUT ROM count is reduced for Kodak image dataset without image quality degradation in histogram equalization for verifications using the presented LUT design methods. According to the image memory compression rate, LUT computation and memory access rate can be significantly reduced.

https://doi.org/10.5573/JSTS.2026.26.1.49

(Sieun Lee) ; (Jong Pal Kim)

A thin flexible neural electrode equipped with a novel fastening mechanism and a body temperature transducer is proposed. Sutures can be typically used to secure electrodes to the nerve. Physicians spend a lot of time and effort securing thin electrodes with sutures. Furthermore, the electrode’s fixation to the nerve can be too loose or too tight. To address these issues, a neural electrode equipped with a plastic deformation element fastening mechanism capable of attaching the electrode to the nerve without using sutures was developed. The novel neural electrode incorporates a latch for auxiliary use during fastening and a titanium wire as a plastic deformation element. The electrode is wrapped around the nerve and then fixed by folding the Ti wire. The fabricated electrode consists of a 15 μm-thick polyimide substrate, a gold pattern for electrical wiring, a thermistor whose resistance varies with temperature, and a 0.2 mm-diameter Ti wire as a plastic deformation element. The fabricated electrode has an impedance of 530 Ω at 1 kHz and a charge storage capacity of 230 μC/cm2 . To evaluate the long-term reliability of the thermistor passivation, the leakage current was maintained at less than 1 nA over 150 days of observation.

https://doi.org/10.5573/JSTS.2026.26.1.60

(Seung-Heon An) ; (Jin-Ku Kang)

This work presents an integrated summer latch (ISL)-based DFE with advantages in low power and enhanced linearity. The proposed architecture enhances linearity by alleviating the equalization variation arising from summing node output differences among high, middle, and low slicers. Furthermore, sharing preamplifiers across the slicers reduces hardware complexity and power consumption. A reduced tap loading scheme is applied to the PAM-4 ISL DFE, enabling low-power operation with 2-tap configuration. Improved energy efficiency with sufficient eye-opening were verified through simulations in a 45nm CMOS process with a 1.1V supply voltage.

https://doi.org/10.5573/JSTS.2026.26.1.69

(Myeongjin Kwak) ; (Jaewoong Jeong) ; (Tae Hee Lee) ; (Do Hoon Lee) ; (Tae-Hyoung Kim) ; (Yongtae Kim)

This paper presents a dual-state hardware accelerator for the ChaCha20 stream cipher, optimized for secure and low-latency communication in connected and automated vehicles (CAVs). The proposed dual-state ChaCha20 (DSCC20) architecture employs an interleaving mechanism that alternately processes two independent states, thereby eliminating idle cycles between column and diagonal rounds and keeping the round hardware fully utilized. With only one additional cycle compared to conventional single-state designs, our DSCC20 achieves substantially higher throughput while incurring minimal hardware overhead. When the design was implemented in Verilog HDL and synthesized using a 28-nm CMOS technology, the DSCC20 delivers 30.06 Gbps throughput and 904.92 Kbps/GE area efficiency at 763 MHz, outperforming baseline and earlier ChaCha20 and AES designs. Compared to software execution on general-purpose CPUs, the DSCC20 further demonstrates a decisive advantage in both throughput and area efficiency. These results confirm that the DSCC20 offers a compact and efficient ChaCha20 accelerator suited for secure and real-time communication in resource-constrained automotive systems.

https://doi.org/10.5573/JSTS.2026.26.1.81

(Dong-Hyeon Kim) ; (Jae-Yoon Oh) ; (Min-Seo Kim) ; (Cheon-Hoo Jeon) ; (Jung-Won Kang) ; (Yong-Seo Koo)

This study proposed a new ESD protection device structure to improve the low holding voltage issue of conventional SCR and LVTSCR devices. The proposed structure incorporates a heavily doped P+ region between the wells to lower the trigger voltage and introduces an additional metal path to form a new discharge route for the parasitic NPN BJT, thereby reducing the positive feedback loop gain and increasing the holding voltage. The operating principle of the proposed device was verified through TCAD simulation, and the design was implemented using a 0.18 μm BCD process. The results confirmed that the proposed device exhibits a higher holding voltage compared to conventional SCR and LVTSCR structures under identical conditions. Consequently, the proposed ESD protection device is suitable for protecting IC circuits operating at 5 V. In addition, an extra PNP BJT discharge path was added at the anode to enhance the current driving capability. TLP measurement results showed that the Ron value decreased, leading to an increase in It2 , confirming that this design effectively improves the current handling capability. Finally, the design parameter D1 was introduced to investigate the electrical characteristics with respect to length variation.As D1 increased, the holding voltage was further improved, which was attributed to the reduction in current gain (β) and loop gain of the parasitic PNP BJT.Therefore, optimizing the length of D1 was found to be an effective design approach that directly contributes to enhancing the holding voltage of the device.