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Volume 10, Number 2, June 2010(ISSN 1598-1657) |
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A Pulsed Id -Vg methodology and Its Application to the Electron Trapping Characterization of High- gate Dielectrics
Chadwin D. Young, Dawei Heh, Rino Choi, Byoung Hun Lee, and Gennadi Bersuke |
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79 |
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Extraction of Exact Layer Thickness of Ultra-thin Gate Dielectrics in Nanoscaled CMOS under Strong Inversion
Munmun Dey and Sanatan Chattopadhyay |
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100 |
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A Subthreshold Swing Model for Symmetric Double-Gate (DG) MOSFETs with Vertical Gaussian Doping
Pramod Kumar Tiwari and S. Jit |
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107 |
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A Low Vth SRAM Reducing Mismatch of Cell-Stability with an Elevated Cell Biasing Scheme
Hiroyuki Yamauchi |
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118 |
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Effect of Counter-doping Thickness on Double-gate MOSFET Characteristics
George James T, Saji Joseph, and Vincent Mathew |
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130 |
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Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs
Kwan Young Kim, Jae Man Jang, Dae Youn Yun, Dong Myong Kim, and Dae Hwan Kim |
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134 |
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Simulation and Modelling of the Write/Erase Kinetics and the Retention Time of Single Electron Memory at Room Temperature
Aïmen Boubaker, Nabil Sghaier, Abdelkader Souifi, and Adel Kalboussi |
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143 |
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A Semi-analytical Model for Depletion-mode N-type Nanowire Field-effect Transistor (NWFET) with Topgate Structure
Yun Seop Yu |
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152 |
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Non-Quasi-Static RF Model for SOI FinFET and Its Verification
In Man Kan |
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160 |
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A Publication of the Institute of Electronics Engineers of Korea |
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