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Volume 9, Number 1, March 2009 (ISSN 1598-1657) |
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SPECIAL ISSUE ON THE 2008 INTERNATIONAL SOC DESIGN CONFERENCE |
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Foreword Hong June Park |
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Editorial Jinyong Chung and Sungjoo Yoo |
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Design of 32 bit Parallel Processor Core for High Energy Efficiency using Instruction-Levels Dynamic Voltage Scaling Technique
Yil Suk Yang, Tae Moon Roh, Soon il Yeo, Woo H. Kwon, and Jongdae Kim |
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1 |
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Timing Analysis of Discontinuous RC Interconnect Lines
Taehoon Kim, Youngdoo Song, and Yungseon Eo |
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A Low-Voltage High-Speed CMOS Inverter-Based Digital Differential Transmitter with Impedance Matching Control and Mismatch Calibration
Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, and Hong-June Park |
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14 |
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A Fast RSSI using Novel Logarithmic Gain Amplifiers for Wireless Communication
Sungho Lee, Yonghoon Song, and Sangwook Nam |
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22 |
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Clock Scheduling and Cell Library Information Utilization for Power Supply Noise Reduction
Yooseong Kim, Sangwoo Han, and Juho Kim |
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29 |
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A Scaling Trend of Variation-Tolerant SRAM Circuit Design in Deeper Nanometer Era
Hiroyuki Yamauchi |
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37 |
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Characteristics of p-Cu2O/n-Si Heterojunction Photodiode made by Rapid Thermal Oxidation
Raid A. Ismail |
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51 |
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Extraction of Ballistic Parameters in 65 nm MOSFETs
Junsoo Kim, Jaehong Lee, Yongmin Kwon, Byung-Gook Park, Jong Duk Lee, and Hyungcheol Shin |
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55 |
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Investigation of Frequency Dependent Sensitivity of Noise Figure on Device Parameters in 65 nm CMOS
MinSuk Koo, Hakchul Jung, HeeSauk Jhon, Byung-Gook Park, Jong Duk Lee, and Hyungcheol Shin |
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61 |
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Monte Carlo Simulation of Ion Implantation Profiles Calibrated for Various Ions over Wide Energy Range
Kunihiro SUZUKI, Yoko TADA, Yuji KATAOKA, and Tsutomu NAGAYAMA |
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67 |
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A Publication of the Institute of Electronics Engineers of Korea |
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