https://doi.org/10.5573/JSTS.2025.25.4.335

(Jounghoon Lim) ; (Jong Pal Kim)

An ultra-low power consumption body temperature circuit for electroceuticals is proposed. Electroceuticals implanted in the body for nerve signal measurement and nerve stimulation can cause short-term or long-term infections, so it is necessary to monitor temperature increases due to inflammation. A Wheatstone bridge is used to read the resistance value of the thermistor mounted on the neural electrode interface. To reduce the current consumption, a dynamic Wheatstone bridge technique is proposed. The current is supplied only for a short time to obtain the temperature information, and the temperature information is obtained once from the bridge in the order of the external thermistor and the built-in resistor, and the temperature information is obtained again by flipping the bridge in the order of the built-in resistor and the external thermistor. Temperature information sampled over a short period of time is stored in the S&H block for use by the VCO in the rear end. The following VCO and TDC both operate at 0.6 V for low power consumption. The post-layout simulation results showed a sensitivity of 2230 digits/degree and a nonlinear error of ?0.05/+0.08?C in the 34 to 42?C range, satisfying the ASTM thermometer standards. Power consumption was 112 nW, which is small enough to be incorporated into implantable devices.

https://doi.org/10.5573/JSTS.2025.25.4.346

(Byeongcheol Kim) ; (Wooyoung Jo) ; (Sangjin Kim) ; (Soyeon Um) ; (Hoi-Jun Yoo)

This paper introduces a novel computing-in-memory (CIM) processor designed for processing deep neural networks (DNNs) with mixed precision, overcoming the limitations of previous CIM architectures that employed bit-serial operations for multi-bit data. The proposed solution, termed the mixed-mode mixed-precision CIM (mixed-CIM) processor, integrates two main features for enhanced energy efficiency: first, the mixed-CIM architecture, which improves energy efficiency by 55.5% compared to prior approaches; second, a digital CIM approach for in-memory multiply-and-accumulate (MAC) operations that boosts throughput by 41.3%. The processor, developed using 28 nm CMOS technology with an area of 1.96 mm2 , achieves an energy efficiency of 85.7 TOPS/W while maintaining 77.4% accuracy on CIFAR100 with ResNet18.

https://doi.org/10.5573/JSTS.2025.25.4.355

(Sangmyoung Lee) ; (Seryeong Kim) ; (Soyeon Kim) ; (Soyeon Um) ; (Sangjin Kim) ; (Sanyeob Kim) ; (Wooyoung Jo) ; (Hoi-jun Yoo)

Spiking Neural Network (SNN) Computing-In-Memory (CIM) achieves high macro-level energy efficiency but struggles with system-level efficiency due to excessive external memory access (EMA) caused by intermediate activation memory demands. To address this, a high-capacity SNN-CIM capable of managing large weight loads is essential. This paper introduces a high-density 1T1C eDRAM-based SNN-CIM processor that significantly enhances system-level energy efficiency through two key features: a high-density, low-power Reconfigurable Neuro-Cell Array (ReNCA) that reuses the 1T1C cell array and employs a charge pump, achieving a 41% area and 90% power reduction and a reconfigurable CIM architecture with dual-mode ReNCA and Dynamic Adjustable Neuron Link (DAN Link) to optimize EMA for activations and weights. These innovations collectively improve system-level energy efficiency by 10×, setting a new benchmark for performance.

https://doi.org/10.5573/JSTS.2025.25.4.363

(Donghui Lee) ; (Yongtae Kim)

Stochastic computing (SC) allows error tolerance design and the ability to perform complex binary operations using simple digital logic circuits, advantageous for low-power design. However, it requires a longer computation time for higher accuracy. To address this, we propose a novel random number generator (RNG) that produces multiple random numbers simultaneously, reducing computation time through parallel processing while achieving lower hardware resource consumption compared to conventional parallel RNG. Our design uses fixed upper bits and a single RNG to generate multiple random numbers in parallel. This approach demonstrates computation speeds up to 64 times faster than conventional methods while reducing area and power by up to 68.2% and 81.9%, respectively, when implemented in 65-nm CMOS technology. Furthermore, we prove the efficacy of our proposed design in digital image processing applications.

https://doi.org/10.5573/JSTS.2025.25.4.375

(Xu She) ; (Yisha Xie) ; (Lintao Liu) ; (Aiying Guo)

This brief presents a low-jitter Phase-Locked Loop (PLL) with dual paths and a negative Kv VoltageControlled Oscillator (NKvVCO) for a Wi-Fi 7 transceiver. The PLL employs a dual-path architecture to ensure robust lock retention under dramatic temperature variations, maintaining phase lock without loss of synchronization. Additionally, the design extends the tuning range of the charge pump (CP) while mitigating phase noise and preventing phase margin deterioration. Analytical expressions and simulations are derived to characterize the performance of this approach. In the locked state, the charge pump operates in a half-CP mode to achieve improved linearity and reduced phase noise. A negative Kv Voltage-Controlled Oscillator (NKvVCO) is used to overcome the limited control voltage range in a 22-nm Fully-Depleted Silicon-On-Insulator (FD-SOI) process. Prototyped in a 22-nm FD-SOI technology, the 7.5-9.6 GHz PLL demonstrates a spur of less than -65 dBc and a root-mean-square (rms) jitter of 57 fs.

https://doi.org/10.5573/JSTS.2025.25.4.384

(Bhuvana B P) ; (Prathiba A) ; (Kanchana Bhaaskaran V S)

Over the past few years, the demand for energy efficient and secure Internet of Things (IoT) devices has surged to a greater extent. Hardware cryptographic modules are being widely employed in IoT devices which are vulnerable to power analysis (PA) attacks. The non-linear multiplicative inverse unit employed in S-box has been majorly identified for purpose of analyzing the susceptibility of cryptographic modules against PA attacks. In this paper, the multiplicative unit of S-Box circuit is designed using positive feedback symmetric adiabatic logic (PFSAL). Energy efficiency of PFSAL is discussed and validated by comparison with the commonly employed adiabatic logic circuits, such as SQAL (secure quasi adiabatic logic), CSSAL (charge sharing symmetric adiabatic logic), FinSAL (FinFET based secure adiabatic logic) and EE-SPFAL (energy efficient symmetric positive feedback adiabatic logic). Further, the security characteristics of PFSAL based multiplicative circuit proves its resilience against PA attacks. Circuits have been designed and simulated using FinFET 32 nm BSIMCMG model files using Cadence®Virtuoso EDA tools. Spice simulations show the proposed PFSAL based circuit is 57%, 59%, and 12% more energy efficient than FinFET based SQAL, CSSAL and FinSAL counterparts.

https://doi.org/10.5573/JSTS.2025.25.4.397

(Boseong Park) ; (Soonseong Hong) ; (Hyouk-Kyu Cha)

This paper proposes a wide input range, low-noise neural recording amplifier IC with adaptive gain control and a feedback-based common-mode cancellation loop (CMCL) for bidirectional neuromodulation applications. The proposed amplifier operates with maximum gain and excellent noise performance under normal conditions, while automatically reducing its gain to extend the dynamic range (DR) and activating the CMCL in response to differential-mode (DM) and common-mode (CM) stimulation artifacts, respectively, thereby adjusting the DM gain to prevent amplifier saturation and removing the CM component. The total harmonic distortion (THD) of the circuit output is 0.822% with a 77 mVPP DM input at a gain of 17.72 dB and 0.418% in the presence of a 1 VPP CM artifact. Under ideal conditions, the amplifier maintains a gain of 40 dB with an input-referred noise (IRN) performance of 2.32 μVrms over a bandwidth of 1 Hz to 10 kHz. The CMCL dynamically toggles on or off depending on the presence of artifacts to balance noise performance and artifact tolerance. The proposed amplifier is designed using 180 nm CMOS process, consumes 2 μW at 1-V supply, and occupies 0.36 mm² of die area.

https://doi.org/10.5573/JSTS.2025.25.4.406

(Yuseong Lee) ; (Jaehak Kang) ; (Jongmin Lee)

In the era of AI and IoT, securing sensitive data is paramount, especially for resource-constrained edge devices. This paper presents a novel lightweight Advanced Encryption Standard (AES)-256 accelerator design that optimizes encryption and decryption processes for low-cost hardware security. By reordering the processing steps in the AES round function and introducing a pre-processing technique in the key expansion process, the proposed architecture enhances both throughput and resource efficiency. Our work results demonstrate that the proposed architecture achieves a throughput of 42.667 Gbps with an area efficiency of 233.69 Kbps/GE. This makes the proposed design an ideal solution for modern IoT devices, where high-speed secure data processing and hardware efficiency are critical.

https://doi.org/10.5573/JSTS.2025.25.4.414

(Deokgi Kim) ; (Jaehyun Noh) ; (Wooyeol Choi) ; (Dongha Shim)

This paper presents a biased poly-gate-separated Schottky barrier diode (biased PGS-SBD). The polygate of PGS-SBD is biased to improve DC (leakage current) or RF performance (cut-off frequency). The operation principles are analyzed using TCAD simulations. The device is fabricated in a 130-nm CMOS process without any process modification. The DC and RF performances are measured and analyzed. The leakage current is reduced from 2.4 × 10?5 to 2.1 × 10?6 mA/μm2 as the poly-gate voltage decreases from +1.0 V to ?1.0 V at the diode voltage of ?1 V. The cut-off frequency increases from 0.75 to 1.25 THz as the gate voltage increases from ?1.0 V to +1.0 V. The proposed device achieved ∼5X lower leakage current or 34% higher cut-off frequency than that of the floating-gate PGS-SBD by controlling the poly-gate voltage.

https://doi.org/10.5573/JSTS.2025.25.4.420

(Gihong Park) ; (Jung Nam Kim) ; (Jun Hui Park) ; (Suk-Kang Sung) ; (Garam Kim) ; (Yoon Kim)

This study presents a modeling approach for the current-voltage (I-V) characteristics of 3D-NAND flash memory using the BSIM-CMG (GEOMOD=3) transistor model combined with a genetic algorithm-based parameter optimization technique. Reference data were extracted from technology computer-aided design (TCAD) simulations for structures with one, three, and five word-line (WL) layers, and these data were utilized to optimize the parameters of the BSIM-CMG model. The results demonstrate that the I-V characteristics of 3D-NAND strings with up to 500 layers can be effectively represented, capturing variations in the I-V curves depending on the WL position on both linear and logarithmic scales. Furthermore, the current-voltage characteristics of tapered channel hole structures were successfully modeled. This work provides a robust framework for accurately simulating the electrical behavior of advanced 3D-NAND flash memory devices.

https://doi.org/10.5573/JSTS.2025.25.4.427

(Yonghwan Lee) ; (Sengjun Jo) ; (Kuduck Kwon)

A 4.8-7.2 GHz low-power noise-cancelling common-gate (CG)-common-source (CS) balun-low-noise amplifier (LNA) is proposed for IEEE 802.11be Wi-Fi applications. The CS amplifier enhances gm by utilizing a current-reused inverter-type amplifier while simultaneously performing a current-bleeding function through a PMOS amplifier. This ensures equal DC currents at the differential output, enabling the use of a balanced load. Additionally, local feedback increases the overall gm of the CG stage by the loop gain, thereby reducing both current consumption and supply voltage requirements. Furthermore, the cross-coupled cascode stage acts as a differential current balancer, mitigating gain and phase mismatches at the differential output. Simulated in a 28-nm CMOS process, the designed balun-LNA achieves a minimum noise figure of 2.74 dB, a maximum voltage gain of 24.6 dB, and input-referred third-order intercept point of ?4.84 dBm. It consumes 3.5 mA from a nominal supply voltage of 0.8 V. Its active die area is 0.079 mm2 .

https://doi.org/10.5573/JSTS.2025.25.4.435

(U-Yeol Seo) ; (Dong-Hyeon Kim) ; (Jae-Yoon Oh) ; (Min-Seo Kim) ; (Yong-Seo Koo)

In this paper, we investigate a technique that integrates a PNP bipolar junction transistor (BJT) to reduce the trigger voltage of a 4H-SiC-based Gate-Grounded NMOS (GGNMOS). The proposed ESD protection circuit lowers the trigger voltage by adding a P+ region to the conventional GGNMOS structure and prevents leakage current by connecting the gate electrode, which was previously linked to the cathode, to the PNP BJT. Through this design, the discharge operation and reliability of the 4H-SiC-based ESD protection circuit are enhanced, while the wide snapback characteristics are improved. To compare and analyze the current discharge behavior of the proposed ESD protection circuit, the electrical characteristics of the device were measured using a Transmission Line Pulse (TLP) test system. Additionally, the measurement results were analyzed based on variations in the design parameter D1(Spacing between N+ and P+ at the anode terminal), and the electrical characteristics under temperature variations were examined to verify the thermal reliability of the 4H-SiC-based ESD protection circuit.

https://doi.org/10.5573/JSTS.2025.25.4.441

(Ji-Woo Kim) ; (Sang-Gyu Park)

This paper presents a 2-bit/cycle second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a floating inverter amplifier (FIA)-based ring amplifier (FBRA) and offset-calibrated comparators. The proposed ADC employs a 2-bit/cycle structure for high-speed operation, utilizing a reference capacitive digital-to-analog converter (CDAC), a signal CDAC, and three comparators. To mitigate the degradation of the signal-to-noise-and-distortion ratio (SNDR) caused by the different offset voltages of multiple comparators, an offset calibration circuit is designed. A cascade of integrators with feedforward (CIFF) structure is designed using an active integrator with an FBRA. The proposed ADC is designed in a 28-nm process with 1-V power supply. The SPICE simulation results show that the ADC achieves an SNDR of 71 dB with a power consumption of 3.2 mW, when operated with a sampling rate of 400-MS/s and an oversampling ratio (OSR) of 8 resulting in a Schreier figure-of-merit (FoM) of 172 dB.

https://doi.org/10.5573/JSTS.2025.25.4.451

(Juntae Park) ; (Dahun Choi) ; (Hyun Kim)

The deployment of compact convolutional neural network (CNN) models with skip connections on edge devices through dedicated hardware accelerators is increasingly prevalent. However, optimizing the use of limited on-chip memory (OCM) across multiple CNN layers, especially those with skip connections, remains a challenge. In this paper, we propose a novel CNN accelerator technique that reorders the computation sequence for each layer to maximize data reuse within the OCM, thereby minimizing DRAM access and improving the utilization of both the OCM and the convolution processor. Additionally, we introduce a shared buffer design that efficiently manages OCM usage across different layers, particularly those involving skip connections. Finally, we present a ResNet-18 accelerator IP, RADAR, implemented with the proposed technique on a Xilinx ZCU102 FPGA. RADAR achieves 64.9 GOPS/W and 446.9 GOPS while maintaining high accuracy, demonstrating significant improvements over prior works in terms of the trade-off between throughput, hardware resource efficiency, and model accuracy.

https://doi.org/10.5573/JSTS.2025.25.4.459

(Hoon Hwi Lee) ; (Min Jae Kim) ; (Jun Woo You) ; (Hyung Jun Jang) ; (Won Woo Ro)

The CXL interface enhances scalability for memory expansion, which is crucial for the demands of emerging memory-intensive applications. However, mismatches between traditional memory hierarchies and CXLenabled memory, particularly when using SSDs as memory space, present critical issues that have not previously been addressed. This paper investigates the deployment of CXL technology in SSDs and the associated data management challenges that differ from those in traditional memory systems. We explore the potential issues of utilizing SSDs as system memory via CXL interfaces, emphasizing the substantial performance bottlenecks caused by bypassing traditional DRAM caching, which leads to CPU resource contention, unintended adverse effects on DRAM, and inefficiencies in SSD access. Based on our findings, we propose improvements to mitigate such challenges by optimizing memory management strategies and system architecture implementations to leverage CXL-enabled SSDs’ capabilities fully.